The present invention relates generally to wireless charging and, more particularly, to a wireless charger using frequency aliasing FSK (Frequency Shift Keying) demodulation.
Frequency shift keying is a frequency modulation scheme in which digital information can be transmitted by discrete changes of a carrier wave frequency. A simple form of FSK is binary frequency shift keying (BFSK) where a logical “1” is represented by a first frequency (fOP) of a carrier wave and a logical “0” is represented by a second frequency (fMOD) of the carrier wave.
One known method for de-modulating BFSK signals uses a comparator to resolve the incoming modulated waveform into a square wave by comparing the received signal amplitude with a threshold. A counter/timer circuit monitors the frequency of state transactions of the square waves in order to determine a count of transitions per time period. In an alternative method, the counter/timer circuit measures how long it takes to complete a pre-defined number of transitions. A decision device then selects a frequency from a predetermined set of frequencies that most closely corresponds to the measurement, and decodes a bit value ‘0’ or ‘1’ corresponding to the selected frequency.
This de-modulation method works satisfactorily when there is an appreciable difference between the modulation frequencies (fOP) and (fMOD). However, when the difference (fOP-fMOD) between the modulation frequencies (fOP) and (fMOD) represents a small fraction (e.g., <1%) of the modulation frequencies (fOP) and (fMOD), detecting such a relatively small frequency shift between the two frequencies (fOP) and (fMOD) is difficult to achieve.
The Wireless Power Consortium WPC-QI standard employs a FSK modulation/demodulation implementation in which modulation frequencies of, for example, fOP=100 kHz and fMOD=100.3 kHz are used. As such, the difference between the modulation frequencies (fOP and fMOD) is 0.3 kHz, representing just 0.3% of the modulation frequencies (fOP and fMOD).
In a conventional counter/timer-based FSK demodulation circuit, in order to detect such a small frequency shift, an accurate high-speed clock signal is required, which in low cost applications can be prohibitively expensive to implement. For example, in order to detect a 0.3 kHz frequency shift between modulation frequencies of fOP=100 kHz and fMOD=100.3 kHz, such as that defined by the WPC-QI standard, using the conventional circuitry described above would require a counter/timer clock running at around 128 MHz. Furthermore, circuits operating at such high frequencies consume significantly more power than lower frequency circuits. As such, implementing such a high frequency clock signal can have a significant detrimental effect on the power efficiency of a device.
Thus it would be advantageous to provide a method and apparatus for performing FSK demodulation that alleviates the need for a high-speed clock signal in order to detect small frequency shifts that represent a small fraction of the fundamental modulation frequencies.